The present invention relates to a MRAM configuration having a memory chip which, between a voltage supply and a memory cell array, has a voltage stabilizer device. The voltage stabilizer device supplies a fixed operating voltage to the memory cell array via word and/or bit lines, in which case a voltage drop occurs between the input of the word and/or bit lines which are connected to the voltage stabilizer device and the output of the lines.
A memory cell is programmed by application of a magnetic field. In order to program a memory cell to a value xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, the magnetic field must exceed certain threshold values.
A problem that generally arises in MRAMs resides in the relatively high power or energy consumption. The latter is due to the fact that the voltage drop along a MRAM cell generally does not exceed 0.5 V for technological reasons. This inherently has the advantage that the word lines and bit lines operate at a relatively low voltage of 0.5 V, for example. However, the supply voltage on a memory chip is significantly higher, being 2 to 3 V, in particular. For this reason, in the existing MRAM configurations, a voltage stabilizer device is provided between the voltage supply of 2 to 3 V and the actual memory cell array with the word lines and the bit lines. The voltage stabilizer device transforms the supply voltage of 2 to 3 V into 0.5 V, which is then impressed on the word line via a word line driver. The rest of the word lines are provided with corresponding voltage stabilizer devices.
Since there is a voltage drop of 0.5 V on each word line in the memory cell array, 0 V are then present at the output of the word lines.
The transformation of the supply voltage of 2 to 3 V into 0.5 V results in that the majority of the energy or power is xe2x80x9cwastedxe2x80x9d, since, of the 2 to 3 V of supply voltage that are made available to the voltage stabilizer device, merely 0.5 V, that is to say between 16% and 25%, is actually utilized, while the remaining 84 to 75% is unutilized.
For understandable reasons, such an energy or power balance is extremely unsatisfactory and should be avoided if possible. Nevertheless, hitherto there has not been a solution to this problem, since the MRAM cells indeed require only about 0.5 V, while the general memory chip voltage supply has values of 2 to 3 V.
It is accordingly an object of the invention to provide a MRAM configuration that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the memory chip voltage supply is better utilized, so that practically no power losses occur.
With the foregoing and other objects in view there is provided, in accordance with the invention, a magnetoresistive random access memory (MRAM) configuration containing a memory chip. The memory chip is formed of lines including bit lines and word lines and a memory cell array subdivided into a plurality of memory cell blocks and connected to the lines running through the memory cell array. The bit lines and word lines running through the memory cell blocks have input sides and output sides with regards to each of the memory cell blocks. A voltage stabilizer device is provided and receives a supply voltage. The voltage stabilizer device is connected to at least one of the bit lines and the word lines. The at least one of the bit lines and the word lines connected to the voltage stabilizer device functions as supply lines supplying fixed operating voltages to the memory cell array. A voltage drop occurs between the input sides of the supply lines and the output sides of the supply lines running through each of the memory cell blocks. The voltage stabilizer device has a plurality of voltage stabilizers and each of the memory cell blocks is respectively connected to one of the voltage stabilizers. The voltage stabilizers are connected to the supply lines and supply the memory cell blocks with the fixed operating voltages that differ from one another in each case.
In the case of a MRAM configuration of the type mentioned in the introduction, the object is achieved according to the invention by virtue of the fact that the memory cell array is subdivided into a plurality of memory cell blocks and the voltage stabilizer device supplies the memory cell blocks with fixed operating voltages that differ from one another in each case. In this case, the voltage stabilizer device may contain a plurality of voltage stabilizers and each memory cell block may be respectively assigned a voltage stabilizer. Preferably, the output of the word and/or bit lines of a first memory cell block, as a voltage supply, is connected to the input of the voltage stabilizer of a second memory cell block, and so on.
Thus, according to the invention, the MRAM configuration is subdivided into a plurality of memory cell blocks, in each individual memory cell block the word lines and the bit lines being driven by operating voltages that differ from the other memory cell blocks.
In accordance with an added feature of the invention, the memory cell blocks include a first memory cell block and a second memory cell block. The voltage stabilizers each have an input and a respective output side of a respective supply line of the first memory cell block is connected to the input of a respective voltage stabilizer connected to the second memory cell block and supplies the supply voltage to the input of the respective voltage stabilizer.
In accordance with another feature of the invention, controlled word line drivers are provided, and one of the controlled word line drivers is disposed between each of the voltage stabilizers and each of the memory cell blocks.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a MRAM configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.